Integrated circuit structures have field oxide grown on the surface of a semiconductor substrate to provide oxide isolation between active regions formed on the semiconductor substrate. The isolation is performed by masking the active regions of the substrate and then oxidizing the remaining portions of the substrate. For example, when growing an oxide layer of a particular thickness, the oxide growth will extend down into the substrate about one-half the total thickness and also extend about one-half the total thickness above the original semiconductor substrate surface. Such a technique, called local oxidation of silicon (LOCOS), is widely used in the semiconductor industry.
An advanced integrated circuit fabrication technique, called shallow trench isolation (STI), is used in forming planar integrated circuit topographies. In the STI manufacturing process, a silicon trench is etched and then filled with a non-conducting material such as oxide. A planarization step is performed to remove the previously deposited oxide from the top of the active areas while keeping the silicon trenches filled with oxide. The active areas are then ready to have active devices built on them while the oxide filled trench regions provide electrical isolation. U.S. Pat. No. 4,954,459, which is assigned to the same assignee as the present application, describes a planarization method using a reverse etch mask to etch away oxide present in the active areas to achieve a first order planarization which is then followed by a chemical and mechanical polish (CMP) to complete the planarization process.
While the conventional manufacturing methods described above provide planarized structures, they are not well suited to provide the small planarized active regions required in present IC structure.